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ir3506 page 1 of 21 v3.02 data sheet xphase3 tm ddr & vtt phase ic description the ir3506 phase ic combined with ir3522 xphase3 tm control ics implements a full featured ddr3 power solution. the ir3522 provides control functions for both the vddr and vtt power rails and interfaces w ith any number of ir3506 phase ics each driving and monitor ing a single phase to power any number of ddr3 dimms. the xphase3 tm architecture delivers a power supply that is small er, more flexible, and easier to design while providing higher efficiency than conve ntional approaches. features power state indicator (psi) interface provides the capability to maximize efficiency at light loads anti-bias circuitry 7v/2a gate drivers (4a gatel sink current) support loss-less inductor current sensing phase delay dff bypassed during psi assertion mode to improve output ripple performance over-current protection during psi assertion mode operation integrated boot-strap synchronous pfet only four ic related external components per phase 3 wire analog bus connects control and phase ics ( vdac, error amp, iout) 3 wire digital bus for accurate daisy-chain phase timing control without external components debugging function isolates phase ic from the conv erter self-calibration of pwm ramp, current sense amplif ier, and current share amplifier single-wire bidirectional average current sharing soft-stop turn-off to insure vddr and vtt tracking small thermally enhanced 16l 3 x 3mm mlpq package rohs compliant application circuit ccs cvccl csin- 15 psi 13 eain 16 iout 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3506 phase ic u1 cbst rcs u12 cin u11 l vout- vout+ 12v vccl 7 wire bus to control ic cout downloaded from: http:///
ir3506 page 2 of 21 v3.02 ordering information part number package order quantity ir3506mtrpbf 16 lead mlpq (3 x 3 mm body) 3000 per reel * IR3506MPBF 16 lead mlpq (3 x 3 mm body) 100 piece strips * samples only absolute maximum ratings stresses beyond those listed below may cause perman ent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. operating junction temperature?????.. 0 o c to 150 o c storage temperature range???????.-65 o c to 150 o c msl rating???????????????2 reflow temperature???????????.260 o c note: 1. maximum gateh ? sw = 8v 2. maximum boost ? gateh = 8v pin # pin name v max v min i source i sink 1 iout 8v -0.3v 1ma 1ma 2 dacin 3.3v -0.3v 1ma 1ma 3 lgnd n/a n/a n/a n/a 4 phsin 8v -0.3v 1ma 1ma 5 phsout 8v -0.3v 2ma 2ma 6 clkin 8v -0.3v 1ma 1ma 7 pgnd 0.3v -0.3v 5a for 100ns, 200ma dc n/a 8 gatel 8v -0.3v dc, -5v for 100ns 5a for 100ns, 200ma dc 5a for 100ns, 200ma dc 9 vccl 8v -0.3v n/a 5a for 100ns, 200ma dc 10 boost 40v -0.3v 1a for 100ns, 100ma dc 3a for 100ns, 100ma dc 11 gateh 40v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc 3a for 100ns, 100ma dc 12 sw 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc n/a 13 psi 8v -0.3v 1ma 1ma 14 csin+ 8v -0.3v 1ma 1ma 15 csin- 8v -0.3v 1ma 1ma 16 eain 8v -0.3v 1ma 1ma downloaded from: http:///
ir3506 page 3 of 21 v3.02 recommended operating conditions for reliable opera tion with margin 4.75v v ccl 7.5v, 0.5v v(dacin) 1.6v, 250khz clkin 9mhz, 250khz phsin 1.5mhz, 0 o c t j 125 o c electrical characteristics the electrical characteristics table list the sprea d of critical values that are guaranteed to be with in the recommended operating conditions (unless otherwise specified). typical values represent the median val ues, which are related to 25c. c gateh = 3.3nf, c gatel = 6.8nf (unless otherwise specified). parameter test condition min typ max unit gate drivers gateh source resistance boost ? sw = 7v. note 1 1. 0 2.5 gateh sink resistance boost ? sw = 7v. note 1 1.0 2.5 gatel source resistance vccl ? pgnd = 7v. note 1 1 .0 2.5 gatel sink resistance vccl ? pgnd = 7v. note 1 0.4 1.0 gateh source current boost=7v, gateh=2.5v, sw=0v. 2.0 a gateh sink current boost=7v, gateh=2.5v, sw=0v. 2.0 a gatel source current vccl=7v, gatel=2.5v, pgnd=0v. 2.0 a gatel sink current vccl=7v, gatel=2.5v, pgnd=0v. 4.0 a gateh rise time boost ? sw = 7v, measure 1v to 4v transition time 5 10 ns gateh fall time boost - sw = 7v, measure 4v to 1v transition time 5 10 ns gatel rise time vccl ? pgnd = 7v, measure 1v to 4v transition time 10 20 ns gatel fall time vccl ? pgnd = 7v, measure 4v to 1v transition time 5 10 ns gatel low to gateh high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gatel falling to 1v to gateh rising to 1v 10 20 40 ns gateh low to gatel high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gateh falling to 1v to gatel rising to 1v 10 20 40 ns disable pull-down resistance note 1 30 80 130 k clock clkin threshold compare to v(vccl) 45 % clkin bias current clkin = v(vccl) -0.5 0.0 0.5 a clkin phase delay measure time from clkin<1v to gateh>1v 40 75 125 ns phsin threshold compare to v(vccl) 35 50 55 % phsout propagation delay measure time from clkin > (vccl * 50% ) to phsout > (vccl *50%). 10pf @125 o c 4 15 35 ns phsin pull-down resistance 30 100 170 k phsout high voltage i(phsout) = -10ma, measure vccl ? phsout 1 0.6 v phsout low voltage i(phsout) = 10ma 0.4 1 v downloaded from: http:///
ir3506 page 4 of 21 v3.02 parameter test condition min typ max unit pwm comparator pwm ramp slope v(vccl) = 6.8 v 46 53 63 mv/ %dc eain bias current 0 eain 3v -5 -0.3 5 a minimum pulse width note 1 55 70 ns current sense amplifier csin+/- bias current -200 0 200 na csin+/- bias current mismatch note 1 -50 0 50 na input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin -1 0 1 mv gain 0.5v v(dacin) < 1.6v 30 32.5 35 v/v unity gain bandwidth c(iout)=10pf. measure at iout. note 1 4.8 6.8 8.8 mhz slew rate 6 v/ s differential input range 0.8v v(dacin) 1.6v, note 1 -10 50 mv differential input range 0.5v v(dacin) < 0.8v, note 1 -5 50 mv common mode input range note 1 0 vccl- 2.5v v rout at t j = 25 o c note 1 2.3 3.0 3.7 k rout at t j = 125 o c 3.6 4.7 5.4 k iout source current 0.500 1.6 2.9 ma iout sink current 0.500 1.4 2.9 ma share adjust amplifier input offset voltage note 1 -3 0 3 mv gain csin+ = csin- = dacin. note 1 3.6 4.7 6.0 v/v unity gain bandwidth note 1 4 8.5 17 khz pwm ramp floor voltage iout unconnected measured relative to dacin -116 0 +116 mv maximum pwm ramp floor voltage iout = dacin - 200mv measured relative to floor voltage. 120 180 240 mv minimum pwm ramp floor voltage iout = dacin + 200mv measured relative to floor voltage -220 -160 -100 mv psi comparator rising threshold voltage note 1 520 620 700 mv falling threshold voltage note 1 400 550 650 mv hysteresis note 1 50 70 120 mv resistance 200 500 850 k floating voltage 800 1150 mv downloaded from: http:///
ir3506 page 5 of 21 v3.02 note 1: guaranteed by design, but not tested in productio n parameter test condition min typ max unit diode emulation preset comparator threshold voltage step v(iout) up until gatel drive s high. compare to v(vccl) -1.0 -0.8 -0.4 v 75 % regulation comparator threshold voltage the ratio of v(csin-) / v(dacin), above which diode emulation cannot occur. 63 74 85 % negative current comparator input offset voltage note 1 -16 0 16 mv propagation delay time step v(csin+) ? v(csin-) fro m positive to negative while v(iout) = vccl. measure time to v(gatel) < 1v. 30 200 380 ns bootstrap diode forward voltage i(boost) = 30ma, vccl=6.8v 360 520 960 mv debug comparator threshold voltage compare to v(vccl) -1.6 -1.4 -1.2 v general vccl supply current 4.2 10 16.1 ma boost supply current 4.75v v ( boost)-v(sw) 8v 0.5 1.5 3 ma dacin bias current -1.5 -0.75 1 a sw floating voltage 0.1 0.3 0.4 ma downloaded from: http:///
ir3506 page 6 of 21 v3.02 pin description pin# pin symbol pin description 1 iout output of the current sense amplifier is con nected to this pin through a 3k resistor. voltage on this pin is equal to v(dacin) + 32.5 [v(csin+) ? v(csin-)]. connecting all iout pins together, a share bus is i mplemented, which provides an indication of the average current being supplied by all the phases. the control ic, for voltage positioning and over-current protection , uses this signal. ovp mode is initiated if the voltage on this pin rises above v( vccl)- 0.8v. 2 dacin reference voltage input from the control ic . the current sense signal and pwm ramp are referenced to the voltage on this pin. 3 lgnd ground for internal ic circuits. ic substrat e is connected to this pin. 4 phsin phase clock input. 5 phsout phase clock output. 6 clkin clock input. 7 pgnd return for low side driver and reference for gateh non-overlap comparator. 8 gatel low-side driver output and input to gateh n on-overlap comparator. 9 vccl supply for low-side driver. internal bootstr ap synchronous pfet is connected from this pin to the boost pin. 10 boost supply for high-side driver. internal boot strap synchronous pfet is connected between this pin and the vccl pin. 11 gateh high-side driver output and input to gatel non-overlap comparator. 12 sw return for high-side driver and reference for gatel non-overlap comparator. 13 psi logic low is an active low (i.e. low = low power state). 14 csin+ non-inverting input to the current sense a mplifier and input to debug comparator. 15 csin- inverting input to the current sense ampli fier and input to synchronous rectification disable comparator. 16 eain pwm comparator input from the error amplifi er output of control ic. downloaded from: http:///
ir3506 page 7 of 21 v3.02 system theory of operation system description the system consists of one control ic (ir3522) and a scalable array of phase converters, each requirin g one phase ic. the control ic communicates with the phase ics usin g three digital buses, i.e., clock, phsin, phsout a nd three analog buses, i.e., dac, ea, iout. the digital buse s are responsible for switching frequency determina tion and accurate phase timing control without any external component. the analog buses are used for pwm contro l and current sharing among interleaved phases. the control ic in corporates all the system functions, i.e., vid, clo ck signals, error amplifier, fault protections, current monitor, etc. the phase ic implements the functions required by the converter of each phase, i.e., the gate drivers, pwm comparator and latch, over-voltage protection, current sensing and sharing, etc. pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 1. voltage mode co ntrol with trailing edge modulation is used. a high-gain wide-bandwidth volt age type error amplifier in the control ic is used for the voltage control loop. the pwm ramp slope will change with t he input voltage and automatically compensate for c hanges in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load c urrent. gnd vout1 vosns1+ dacin vref1 vout1 iin1 vdrp1 lgnd iout phsin vosns1- csin- csin+ gatel eain gateh sw vin fb1 eaout1 clkout clkin phsout pgnd vccl vcch dacin clkin phsout csin+ gatel eain gateh iout phsin sw pgnd vccl vcch csin- phsin phsout vid6 vid6 irosc vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp ifb1 vdrp1 amp vdac clock generator current sense amplifier r s share adjust error amplifier reset dominant pwm latch error amplifier cout ir3522 control ic ir3506 phase ic output 1 only pwm comparator pwm comparator vccl - + + + ramp discharge clamp enable share adjust error amplifier reset dominant pwm latch current sense amplifier r s ir3506 phase ic remote sense amplifier vccl ccs rcs +- cfb1 rcs cbst + - ccs cbst + - + - ccp11 + - + - rfb12 rdrp1 cdrp1 rfb11 3k clk d q + - + - rcp1 + - 3k + - + - ccp12 clk d q + - figure 1: pwm block diagram downloaded from: http:///
ir3506 page 8 of 21 v3.02 frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250khz to 9mhz by an external resistor. the control ic system clock sign al (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output (ph sout) is connected to the phase clock input (phsin) of the f irst phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. and phsout of th e last phase ic is connected back to phsin of the c ontrol ic. during power up, the control ic sends out clock sig nals from both clkout and phsout pins and detects t he feedback at phsin pin to determine the phase number and monitor any fault in the daisy chain loop. fig ure 2 shows the phase timing for a four-phase converter. the switch ing frequency is set by the resistor rosc as shown in figure 9. the clock frequency equals the number of phase times th e switching frequency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 2: four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is sets and the pwm ramp voltage begins to increase. in con junction, the low side driver is turned off and the high side driver is turned on after a non-overlap time. when the pwm ra mp voltage exceeds the error amplifier?s output vol tage, the pwm latch is reset. this turns off the high side driver , turns on the low side driver after the non-overla p time, and activates the ramp discharge clamp. the clamp drives the pwm ramp voltage to a level set by the share adjust amplifi er until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go to a 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error am plifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regar dless of the voltage of the pwm ramp. this arrangem ent guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. i t also favors response to a load step decrease which is appropria te given the low output to input voltage ratio of m ost systems. the inductor current will increase much more rapidly th an decrease in response to load transients. an addi tional advantage of this pwm modulator is that differences in ground or input voltage at the phases have no effect on o peration since the pwm ramps are referenced to vdac. figure 3 depicts pwm operating waveforms under vari ous conditions. downloaded from: http:///
ir3506 page 9 of 21 v3.02 figure 3 pwm operating waveforms lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as show n in figure 4. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the ind uctor current. figure 4 inductor current sensing and current sen se amplifier c o l r l r cs c cs v o current sense amp csout i l v l v cs phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) downloaded from: http:///
ir3506 page 10 of 21 v3.02 the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch currents. t he output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in s eries with the inductor, this is the only sense method that can su pport a single cycle transient response. other meth ods provide no information during either load increase (low side s ensing) or load decrease (high side sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in m any ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and th e output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and ou tput voltage are all additional sources of peak-to- average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 5. it s gain is nominally 32.5 and the 3850 ppm/oc increase in inductor dcr s hould be compensated in the voltage loop feedback p ath. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the control ic an d other phases through an on-chip 3k resistor connected to the iout pin. the iout pins of all the phases are tied together and the voltage on the share bus represents the average cur rent through all the inductors and is used by the c ontrol ic for voltage positioning and current limit protection. t he input offset of this amplifier is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of e rror for the current share loop. in order to achiev e very small input offset error and superior current sharing performan ce, the current sense amplifier continuously calibr ates itself. this calibration algorithm creates ripple on iout bus wi th a frequency of f sw /(32*28) in a multiphase architecture. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared w ith the average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp, thereby increasing its duty cycle and output current. in contrary, if current in a phase is larg er than the average current, the share adjust amplifier of the phase wi ll pull up the starting point of the pwm ramp there by decreasing its duty cycle and output current. the current share am plifier is internally compensated so that the cross over frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. downloaded from: http:///
ir3506 page 11 of 21 v3.02 ir3506 theory of operation block diagram the block diagram of the ir3506 is shown in figure 5, and specific features are discussed in the follo wing sections. eain eain pwm comparator + - + - csin- csin+ debug comparator 0.15v psi 500k 610mv 510mv + - 1v psi comparator 75pct_reg csaout calibration dacin + - irosc irosc current sense amplifier x32.5 + 75% regulation comparator x 0.75 + + - phsin phsin diode emulation preset comparator 0.8v + - vccl de_preset iout diode emulation preset enable latch phase delay non- overlap circuit cal share adjust amplifier + - negative current comparator 3k + - lgnd dacin dacin vccl psi boost gateh sw gate drivers vccl dacin share_adj - + pgnd gatel vccl phsout vccl gatel disable debug off (low=open) pwm 15 cal clkin 1 pwm rmpout calibration pwm reset phsin vccl dacin-share_adj pwm ramp generator gates disable phsin figure 5 block diagram tri-state gate drivers the gate drivers can deliver up to 2a peak current (4a sink current for bottom driver). an adaptive no n-overlap circuit monitors the voltage on the gateh and gatel pins to prevent mosfet shoot-through current while minimizing body diode conduction. the non-overlap l atch is added to eliminate the error triggering cau sed by the switching noise. an enable signal is provided by th e control ic to the phase ic without the addition o f a dedicated signal line. the error amplifier output of the cont rol ic drives low in response to any fault conditio n such as vccl under voltage or output overload. downloaded from: http:///
ir3506 page 12 of 21 v3.02 a synchronous rectification disable comparator is u sed to detect converter csin- pin voltage, which re presents local converter output voltage. if the voltage is b elow 75% of vout1 and negative current is detected during startup, gatel drives low, which disables synchrono us rectification and eliminates negative current du ring power- up. once vout1 reaches approximately 75 % of its n ominal value, synchronous rectification is regain a nd can not be disable again until the startup. the gate drivers pull low if the supply voltages ar e below the normal operating range. an 80k resistor is connected across the gateh/gatel and pgnd pins to prevent the gateh/gatel voltage from rising due to leakage or other causes under these conditions. over voltage protection (ovp) output over-voltage might occur due to a high side mosfet short or if the output voltage sense path is compromised. if the over-voltage protection compara tors sense that either vout1 pin voltage exceeds vr ef1 by 260mv or vout2 exceeds vref1, the over voltage faul t latch is set which pulls the error amplifier outp ut low to turn off the converter power stage. the ir3522 comm unicates an ovp condition to the system by raising the crowbar pin voltage to within v(vccl) ? 0.2 v. wit h the error amplifiers outputs low, the low-side mo sfet turn-on within approximately 150ns. the low side mo sfet will remain low until the over voltage fault c ondition latch cleared. downloaded from: http:///
ir3506 page 13 of 21 v3.02 pwm ramp every time the phase ic is powered up, pwm ramp mag nitude is calibrated to generate a 53 mv/%dc. for example, for a 15 % duty ratio the ramp amplitude i s 795mv. in response to a load step-up, the error amplifier can demand 100 % duty cycle. in order to avoid puls e skipping under this scenario and allow the boost ca p to replenish, a minimum off-time is allowed in th is mode of operation. as shown in figure 6, 100 % duty is detected by comparing the pwm latch output (pwmq) and its input clock (pwm_clk). if the pwmq i s high when the pwm_clk is asserted, the topfet turnoff is initiated. the topfet is again turned on once the rmpout drops within 200 mv of the vdac. phout clkin eain (2 phase design) rmpout pwmq 100 % duty operation normal operation figure 1: pwm operation during normal and 100 % dut y mode. power state indicator (psi) function from a system perspective, the psi input is control led by the system and is forced low when the load c urrent is lower than a preset limit and forced high when l oad current is higher than the preset limit. ir350 6 can accept an active low signal on its psi input and fo rce the drivers into tri-state, effectively forcing the phase ic into off state. a psi-assert signal activates three features in the phase ic. 1) it disconnects the iout pin from the iout bus: f rom a system perspective, iout is used to report cu rrent and is used for over-current protection. by disconn ecting the disabled phase from the iout bus, proper current reporting and over-current protection level is ensured. 2) the dff is disabled and it appears as a pass-thr ough to the daisy chain loop: by removing the dff f rom the daisy chain, the system ensures that proper pha se delay is activated among the active phases. 3) the gate drivers are forced to tri-state, effect ively, disabling the phase ic: figure 7 shows the i mpact of psi-assert on the gate drivers. after 8 cycle phsin delay, at the next clk falling edge, the psi_sync goes from 0 to 1. this disables the gate drives and shor ts the dff. downloaded from: http:///
ir3506 page 14 of 21 v3.02 psi_sync psi 8 phsin delay d_pwm latch clk figure 2: psi assertion. debugging mode if csin+ pin is pulled up to vccl voltage, ir3506 e nters into debugging mode. both drivers are pulled low and iout output is disconnected from the current sh are bus, which isolates this phase ic from other ph ases. however, the phase timing from phsin to phsout does not change. emulated bootstrap diode ir3506 integrates a pfet to emulate the bootstrap d iode. if two or more top mosfets are to be driven a t higher switching frequency, an external bootstrap d iode connected from vccl pin to boost pin may be needed. operation at higher output voltage the proper operation of the phase ic is ensured for maximum output voltage up to vccl-2.5v if the diff erential input (csin(+) ? csin(-)) to current sense amplifie r remain below 30 mv. otherwise, the maximum voltag e output is calculated with the following equation: ), (* 5.1 max _ ? + ? ? ? = csin csin v v gcs vccl vo where, gcs is the current sense amplifier gain (typ ically 32.5). downloaded from: http:///
ir3506 page 15 of 21 v3.02 design procedures - ir3506 inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but does effect the current sig nal iout as well as the output voltage during the load current transient if adaptive voltage positioning is adopte d. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r = (1) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic a 0.1uf-1uf decoupling capacitor is required at the vccl pin. current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loo p so that the interaction between the two loops is eliminated. the crossover frequency of current share loop is approximately 8 khz. downloaded from: http:///
ir3506 page 16 of 21 v3.02 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to the ic. dedicate at least one middle layer for a ground pl ane, which is then split into signal ground plane ( lgnd) and power ground plane (pgnd). separate analog bus (eain, dacin, and iout) from d igital bus (clkin, phsin, and phsout) to reduce the noise coupling. connect pgnd to lgnd pins to their respective grou nd planes through vias. place current sense resistors and capacitors (r cs and c cs ) close to phase ic. use kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon. the wire from the indu ctor terminal to csin- should not cross over the fast tr ansition nodes, i.e. switching nodes, gate drive ou tputs and bootstrap nodes. place the decoupling capacitor c vccl as close as possible to the vccl pin. place the phase ic as close as possible to the mos fets to reduce the parasitic resistance and inductance of the gate drive paths. place the input ceramic capacitors close to the dr ain of top mosfet and the source of bottom mosfet. use combination of different packages of ceramic ca pacitors. there are two switching power loops. one loop incl udes the input capacitors, top mosfet, inductor, output capacitors and the load; another loop consis ts of bottom mosfet, inductor, output capacitors an d the load. route the switching power paths using wid e and short traces or polygons; use multiple vias f or connections between layers. pgnd gatel vccl gateh boost vcc eain to digital bus to inductor to lgnd plane c vccl to vin d bst sw c bst to gate drive voltage phsin lgnd dacin ishare csin - phsout clkin to top mosfet pgnd plane lgnd plane ground polygon c vcc r cs c cs to bottom mosfet to analog bus to switching no de r pgnd gatel vccl gateh boost vcc eain to digital bus to inductor to lgnd plane c vccl to vin d bst sw c bst to gate drive voltage phsin lgnd dacin iout phsout clkin to top mosfet pgnd plane lgnd plane ground polygon c vcc r cs c cs to bottom mosfet to analog bus to switching node csin+ downloaded from: http:///
ir3506 page 17 of 21 v3.02 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) four 0.3mm diameter vias shall be placed in the pa d land spaced at 0.85mm, and connected to ground to minimize the noise effect on the ic, and to tran sfer heat to the pcb no pcb traces should be routed nor vias placed und er any of the four corners of the ic package. doin g so can cause the ic to raise up form the pcb result ing in poor solder joints to the ic leads. downloaded from: http:///
ir3506 page 18 of 21 v3.02 solder resist the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provi de a fillet so a solder resist width of 0.17mm remains. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. the four vias in the land pad should be tented or plugged from bottom board side with solder resist. downloaded from: http:///
ir3506 page 19 of 21 v3.02 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the oc currence of lead shorts. since for 0.5mm pitch dev ices the leads are only 0.25mm wide, the stencil apertur es should not be made narrower; openings in stencil s < 0.25mm wide are difficult to maintain repeatable so lder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. the land pad aperture should be approximately 70% area of solder on the center pad. if too much sold er is deposited on the center pad the part will float and the lead lands will be open. the maximum length and width of the land pad stenc il aperture should be equal to the solder resist op ening minus an annular 0.2mm pull back to decrease the in cidence of shorting the center land to the lead lan ds when the part is pushed into the solder paste. downloaded from: http:///
ir3506 page 20 of 21 v3.02 package information 16l mlpq (3 x 3 mm body) ? ja = 38 o c/w, jc = 3 o c/w downloaded from: http:///
ir3506 page 21 of 21 v3.02 data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . www.irf.com downloaded from: http:///

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